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2012-07-26 rev.1.0 T3GF3WBG 1 cmos digital integrated circuits silicon monolithic T3GF3WBG T3GF3WBG T3GF3WBG T3GF3WBG 1. 1. 1. 1. functional description functional description functional description functional description ? dual-supply bus transceiver for sd memory card 2. 2. 2. 2. general general general general this device is an advanced high-speed dual-supply bus transceiver fabricated with silicon-gate cmos technology. designed for use as an interface between a 1.8-v bus and a 1.8-v/2.9-v bus in mixed 1.8-v/2.9-v supply systems. the a-port interfaces with the 1.8-v bus, the b-port with the 1.8-v/2.9-v bus. the direction of data transmission is determined by the level of the dir input. all inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. 3. 3. 3. features features features features (1) compliant with sd specification part 1 physical layer specification 3.0 (sdr12/sdr25/ddr50) (2) bidirectional interface between 1.8-v and 2.9-v buses (3) high-speed operation: t pd (a to b) = 5.0 ns (max) (v cca = 1.8 0.15 v, v ccb = 2.9 0.1 v) t pd (b to a) = 5.0 ns (max) (v cca = 1.8 0.15 v, v ccb = 2.9 0.1 v) t pd (a to b) = 7.0 ns (max) (v cca = 1.8 0.15 v, v ccb = 1.8 0.1 v) t pd (b to a) = 7.0 ns (max) (v cca = 1.8 0.15 v, v ccb = 1.8 0.1 v) (4) output current: i ohb /i olb = 6 ma (min) (v ccb = 2.8 v) i oha /i ola = 6 ma (min) (v cca = 1.65 v) (5) integrated emi filter on b-port (6) integrated pull-up and pull-down resistors on b-port (7) latch-up performance: 200 ma (8) esd performance: human body model > 2000 v iec61000-4-2 level 4 (contact) > 8 kv (sd card side) iec61000-4-2 level 4 (air) > 15 kv (sd card side) cdm > 500 v (9) ultra-small package: wcsp25
2012-07-26 rev.1.0 T3GF3WBG 2 4. 4. 4. 4. packaging and pin assignment (top view) packaging and pin assignment (top view) packaging and pin assignment (top view) packaging and pin assignment (top view) 4.1. 4.1. 4.1. 4.1. pin assignment pin assignment pin assignment pin assignment a b c d e 1 dat2.h dat3.h clk.h dat0.h dat1.h 2 cmd-dir sel enable cmd.h clk-f 3 dat0-dir v cca gnd cd dat123-dir 4 v batt v ccb gnd cmd-b wp 5 dat2-b dat3-b clk-b dat0-b dat1-b 5. 5. 5. 5. marking marking marking marking fig. fig. fig. fig. 5.1 5.1 5.1 5.1 marking marking marking marking s-ufbga25-0202-0.40-001
2012-07-26 rev.1.0 T3GF3WBG 3 6. 6. 6. 6. principle of operation principle of operation principle of operation principle of operation 6.1. 6.1. 6.1. 6.1. truth table truth table truth table truth table input clk.h l h output clk-f l h output clk-b l h input cmd-dir l h function cmd.h output input function cmd-b input output outputs cmd.h = cmd-b cmd-b = cmd.h input dat0-dir l h function dat0.h output input function dat0-b input output outputs dat0.h = dat0-b dat0-b = dat0.h input dat123-dir l h function dat1.h - dat3.h output input function dat1-b - dat3-b input output outputs datn.h = datn-b datn-b = datn.h input enable l h h h input sel x x l h uvlo x detect release release regulator function off off 2.9 v 1.8 v
2012-07-26 rev.1.0 T3GF3WBG 4 7. 7. 7. 7. block diagram block diagram block diagram block diagram fig. fig. fig. fig. 7.1 7.1 7.1 7.1 block diagram 1 block diagram 1 block diagram 1 block diagram 1 fig. fig. fig. fig. 7.2 7.2 7.2 7.2 block diagram 2 block diagram 2 block diagram 2 block diagram 2 fig. fig. fig. fig. 7.3 7.3 7.3 7.3 block diagram 3 block diagram 3 block diagram 3 block diagram 3
2012-07-26 rev.1.0 T3GF3WBG 5 fig. fig. fig. fig. 7.4 7.4 7.4 7.4 block diagram 4 block diagram 4 block diagram 4 block diagram 4 fig. fig. fig. fig. 7.5 7.5 7.5 7.5 block diagram 5 block diagram 5 block diagram 5 block diagram 5 fig. fig. fig. fig. 7.6 7.6 7.6 7.6 block diagram 6 block diagram 6 block diagram 6 block diagram 6
2012-07-26 rev.1.0 T3GF3WBG 6 8. 8. 8. 8. absolute maximum ratings (note) absolute maximum ratings (note) absolute maximum ratings (note) absolute maximum ratings (note) characteristics supply voltage input voltage (dir, clk.h) input voltage (enable, sel) bus i/o voltage clamp diode current (dir, clk.h) clamp diode current (enable, sel) i/o diode current output current v cc /ground current per supply pin power dissipation storage temperature symbol v cca v batt v in v i/oa v i/ob i ik i i/ok i outa i outb i cca p d t stg note (note 1) (note 2) rating -0.5 to 3.0 5.5 -0.5 to v cca +0.5 -0.5 to 5.5 -0.5 to v cca +0.5 -0.5 to v ccb +0.5 25 -25 25 25 25 50 400 -55 to 150 unit v ma mw note: exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in ic performance or even destruction. using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook ( handling precautions / derating concept and methods ) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). note 1: high (h) or low (l) state. i out absolute maximum rating must be observed. note 2: v out < gnd, v out > v cc 9. 9. 9. 9. operating ranges (note) operating ranges (note) operating ranges (note) operating ranges (note) characteristics supply voltage input voltage (dir, clk.h) input voltage (enable, sel) bus i/o voltage output current operating temperature input rise time input fall time symbol v cca v batt v in v i/oa v i/ob i outa i outb t opr dt/dv note (note 1) test condition v cca = 1.65 to 1.95 v v ccb = 2.8 to 3.0 v, v ccb is supplied from the built-in ldo. v cca = 1.65 v, v ccb = 2.8 v rating 1.65 to 1.95 3.1 to 5.0 0 to v cca 0 to 5.0 0 to v cca 0 to v ccb 6 6 85 0 to 10 0 to 10 unit v ma ns/v note: the operating ranges must be maintained to ensure the normal operation of the device. unused inputs and bus inputs must be tied to either v cc or gnd. please connect both bus inputs and the bus outputs with v cc or gnd when the i/o of the bus terminal changes by the function. in this case, please note that the output is not short-circuited. note: don't input the signal during the period of changing the output voltage of the ldo. note 1: high (h) or low (l) state.
2012-07-26 rev.1.0 T3GF3WBG 7 10. 10. 10. 10. electrical characteristics electrical characteristics electrical characteristics electrical characteristics 10.1. 10.1. 10.1. 10.1. dc characteristics (note) dc characteristics (note) dc characteristics (note) dc characteristics (note) (unless otherwise specified, t (unless otherwise specified, t (unless otherwise specified, t (unless otherwise specified, t a a a a = -30 to 85 = -30 to 85 = -30 to 85 = -30 to 85 , 1.65 v , 1.65 v , 1.65 v , 1.65 v v v v v cca cca cca cca 1.95 v) 1.95 v) 1.95 v) 1.95 v) characteristics high-level input voltage (dir, an) high-level input voltage (bn) low-level input voltage (dir, an) low-level input voltage (bn) high-level output voltage low-level output voltage input leakage current quiescent supply current symbol v iha v ihb v ila v ilb v oha v ohb v ola v olb i in a i in b i cca test condition (note 1) v in = v ih or v il , i oha = -100 a v in = v ih or v il , i oha = -6 ma v in = v ih or v il , i ohb = -100 a v in = v ih or v il , i ohb = -6 ma v in = v ih or v il , i ohb = -4 ma v in = v ih or v il , i ola = 100 a v in = v ih or v il , i ola = 6 ma v in = v ih or v il , i olb = 100 a v in = v ih or v il , i olb = 6 ma v in = v ih or v il , i olb = 4 ma v ina = v cca or gnd dir = high v cd = v wp = v cca v cmd-b , v dat0-b , v dat1-b , v dat2-b = v ccb v dat3-b = gnd, dir = low v cd = v wp = v cca v ina = v cca or gnd dir = high v cd = v wp = v cca v cca (v) 1.65 to 1.95 1.65 1.65 to 1.95 1.65 1.65 to 1.95 v ccb (v) 1.7 to 3.0 2.8 to 3.0 1.7 to 1.9 1.7 to 3.0 2.8 to 3.0 1.7 to 1.9 1.7 to 3.0 2.8 to 3.0 1.7 to 1.9 2.8 1.7 1.7 to 3.0 2.8 to 3.0 1.7 to 1.9 2.8 1.7 1.7 to 3.0 min v cca 0.65 2.0 v ccb 0.65 v cca - 0.2 1.15 v ccb - 0.2 v ccb - 0.2 2.2 1.2 max v cca 0.35 0.8 v ccb 0.35 0.2 0.3 0.2 0.2 0.4 0.3 5.0 5.0 20 unit v a note: v ccb is supplied from the built-in ldo. note 1: an is a host side signal. bn is a card side signal.
2012-07-26 rev.1.0 T3GF3WBG 8 10.2. 10.2. 10.2. 10.2. ac characteristics (note) ac characteristics (note) ac characteristics (note) ac characteristics (note) (unless otherwise specified, t (unless otherwise specified, t (unless otherwise specified, t (unless otherwise specified, t a a a a = -30 to 85 = -30 to 85 = -30 to 85 = -30 to 85 , input: t , input: t , input: t , input: t r r r r = t = t = t = t f f f f = 2.0 ns) = 2.0 ns) = 2.0 ns) = 2.0 ns) 10.2.1. 10.2.1. 10.2.1. 10.2.1. v v v v cca cca cca cca = 1.8 = 1.8 = 1.8 = 1.8 0.15 v, v 0.15 v, v 0.15 v, v 0.15 v, v ccb ccb ccb ccb = 2.9 = 2.9 = 2.9 = 2.9 0.1 v 0.1 v 0.1 v 0.1 v characteristics propagation delay time (bn an) propagation delay time (an bn) propagation delay time (clk.h clk-f) skew (clk-f to cmd/dat) output rise/fall time (an) output rise/fall time (bn) output skew symbol t plh /t phl t skew.f t tlh /t thl t oslh /t oshl note (note 1) test condition see fig. 10.2.1, 10.2.2 see fig. 10.2.1, 10.2.2 see fig. 10.2.3 min 1.0 -1.8 typ. 3.5 3.5 5.7 0.0 1.5 1.5 max 5.0 5.0 9.5 3.0 0.5 unit ns note: an is a host side signal. bn is a card side signal. v ccb is supplied from the built-in ldo. note 1: parameter guaranteed by design. (t oslh = |t plhm - t plhn |, t oshl = |t phlm - t phln |) 10.2.2. 10.2.2. 10.2.2. 10.2.2. v v v v cca cca cca cca = 1.8 = 1.8 = 1.8 = 1.8 0.15 v, v 0.15 v, v 0.15 v, v 0.15 v, v ccb ccb ccb ccb = 1.8 = 1.8 = 1.8 = 1.8 0.1 v 0.1 v 0.1 v 0.1 v characteristics propagation delay time (bn an) propagation delay time (an bn) propagation delay time (clk.h clk-f) skew (clk-f to cmd/dat) output rise/fall time (an) output rise/fall time (bn) output skew symbol t plh /t phl t skew.f t tlh /t thl t oslh /t oshl note (note 1) test condition see fig. 10.2.1, 10.2.2 see fig. 10.2.1, 10.2.2 see fig. 10.2.3 min 1.0 -0.8 typ. 4.5 5.0 8.0 0.4 1.5 1.5 max 7.0 7.0 13.5 1.6 0.5 unit ns note: an is a host side signal. bn is a card side signal. v ccb is supplied from the built-in ldo. note 1: parameter guaranteed by design. (t oslh = |t plhm - t plhn |, t oshl = |t phlm - t phln |) 10.3. 10.3. 10.3. 10.3. dynamic switching characteristics (note) dynamic switching characteristics (note) dynamic switching characteristics (note) dynamic switching characteristics (note) (unless otherwise specified,t (unless otherwise specified,t (unless otherwise specified,t (unless otherwise specified,t a a a a = 25 = 25 = 25 = 25 , input: t , input: t , input: t , input: t r r r r = t = t = t = t f f f f = 2.0 ns, c = 2.0 ns, c = 2.0 ns, c = 2.0 ns, c l l l l = 15 pf) = 15 pf) = 15 pf) = 15 pf) characteristics quiet output maximum dynamic v ol quiet output minimum dynamic v ol quiet output maximum dynamic v oh quiet output minimum dynamic v oh (a b) (b a) (a b) (b a) (a b) (b a) (a b) (b a) symbol v olp v olv v ohp v ohv note (note 1) test condition see fig. 10.3.1 v ih = v cc , v il = 0 v v cca (v) 1.8 v ccb (v) 2.9 typ. 0.35 0.25 -0.35 -0.25 3.25 2.05 2.55 1.55 unit v note: an is a host side signal. bn is a card side signal. note 1: parameter guaranteed by design. 10.4. 10.4. 10.4. 10.4. capacitive characteristics (unless otherwise specified, t capacitive characteristics (unless otherwise specified, t capacitive characteristics (unless otherwise specified, t capacitive characteristics (unless otherwise specified, t a a a a = 25 = 25 = 25 = 25 ) ) ) ) characteristics power dissipation capacitance symbol c pda c pdb note (note 1) test condition a b (dir = high) b a (dir = low) a b (dir = high) b a (dir = low) v cca (v) 1.8 v ccb (v) 2.9 typ. 24 22 76 28 unit pf note 1: c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. average operating current can be obtained by the equation. i cc (opr) = c pd v cc f in + i cc /6 (per bit)
2012-07-26 rev.1.0 T3GF3WBG 9 fig. 10.2.1 parameter for ac test circuit fig. 10.2.1 parameter for ac test circuit fig. 10.2.1 parameter for ac test circuit fig. 10.2.1 parameter for ac test circuit fig. 10.2.2 ac waveform t fig. 10.2.2 ac waveform t fig. 10.2.2 ac waveform t fig. 10.2.2 ac waveform t plh plh plh plh , t , t , t , t phl phl phl phl , t , t , t , t tlh tlh tlh tlh , t , t , t , t thl thl thl thl fig. 10.2.3 ac waveform t fig. 10.2.3 ac waveform t fig. 10.2.3 ac waveform t fig. 10.2.3 ac waveform t oslh oslh oslh oslh , t , t , t , t oshl oshl oshl oshl table table table table 10.2.1 10.2.1 10.2.1 10.2.1 ac waveform symbols ac waveform symbols ac waveform symbols ac waveform symbols v cc 2.9 0.1 v 1.8 0.15 v symbol v ih v m v ih v m value v cc v cc /2 v cc v cc /2 fig. 10.3.1 quiet output measurement circuit v fig. 10.3.1 quiet output measurement circuit v fig. 10.3.1 quiet output measurement circuit v fig. 10.3.1 quiet output measurement circuit v ohp ohp ohp ohp , v , v , v , v ohv ohv ohv ohv , v , v , v , v olp olp olp olp , v , v , v , v olv olv olv olv
2012-07-26 rev.1.0 T3GF3WBG 10 11. 11. 11. 11. regulator section regulator section regulator section regulator section 11.1. 11.1. 11.1. 11.1. electrical characteristics (unless otherwise specified, v electrical characteristics (unless otherwise specified, v electrical characteristics (unless otherwise specified, v electrical characteristics (unless otherwise specified, v in in in in = v = v = v = v out out out out + 1 v, + 1 v, + 1 v, + 1 v, i i i i out out out out = 1 ma, c = 1 ma, c = 1 ma, c = 1 ma, c in in in in = 0.1 = 0.1 = 0.1 = 0.1 f, c f, c f, c f, c out out out out = 2.2 = 2.2 = 2.2 = 2.2 f, t f, t f, t f, t j j j j = 25 = 25 = 25 = 25 ) ) ) ) characteristics supply voltage output voltage uvlo detect voltage uvlo release voltage line regulation load regulation quiescent current standby current output noise voltage temperature coefficient of output voltage ripple rejection high-level input voltage low-level input voltage control current (on) control current (off) startup time transition time (from 2.9 v to 1.8 v) symbol v batt v ccb v uvlo1 v uvlo2 reg line reg load i b(on) i b(off) v n t cvo r.r v ih v il i ct(on) i ct(off) t start t trans note (note 1) test condition sel = low sel = high v out + 0.5 v v in 5.0 v, i out = 1 ma 1 ma i out 100 ma i out = 0 ma v enable = 0 v, v sel = 0 v v in = v out = + 1 v, i out = 10 ma, 10 hz f 100 khz, t a = 25 -30 t opr 85 v in = v out + 1 v, i out = 10 ma, f = 1 khz, v ripple = 500 mv p-p , t a = 25 enable, sel v enable = 1.5 v v enable = 0 v sel = low min 3.1 2.8 1.7 1.5 0 typ. 2.9 1.8 2.4 2.6 3 80 0.1 140 100 40 max 5.0 3.0 1.9 2.7 2.8 15 150 160 1.0 v batt 0.25 7.5 0.1 200 5 unit v mv a vms ppm/ db v a s ms note 1: the relation between the supply voltage and the output voltage is shown in the below figure. this figure shows the representative typical behavior of the ldo. fig. fig. fig. fig. 11.1.1 11.1.1 11.1.1 11.1.1 uvlo characteristics uvlo characteristics uvlo characteristics uvlo characteristics
2012-07-26 rev.1.0 T3GF3WBG 11 11.2. 11.2. 11.2. 11.2. emi filter response (typical performance) emi filter response (typical performance) emi filter response (typical performance) emi filter response (typical performance) fig. fig. fig. fig. 11.2.1 11.2.1 11.2.1 11.2.1 emi filter response (typical performance) emi filter response (typical performance) emi filter response (typical performance) emi filter response (typical performance)
2012-07-26 rev.1.0 T3GF3WBG 12 package dimensions package dimensions package dimensions package dimensions unit: mm weight: 0.006 g (typ.) package name(s) toshiba: s-ufbga25-0202-0.40-001
2012-07-26 rev.1.0 T3GF3WBG 13 restrictions on product use restrictions on product use restrictions on product use restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. toshiba assumes no liability for customers' product design or applications. toshiba assumes no liability for customers' product design or applications. toshiba assumes no liability for customers' product design or applications. ? product is neither intended nor warranted for use in equipments or systems that require product is neither intended nor warranted for use in equipments or systems that require product is neither intended nor warranted for use in equipments or systems that require product is neither intended nor warranted for use in equipments or systems that require extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage and/or serious public impact cause loss of human life, bodily injury, serious property damage and/or serious public impact cause loss of human life, bodily injury, serious property damage and/or serious public impact cause loss of human life, bodily injury, serious property damage and/or serious public impact ("unintended use"). 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